gnd
v dd h
gnd
v dd l
gnd
gnd
gnd
v dd l 181
185
190
195
200
205
210
215
220
225
230
235
240 CXD8818R(1/5)
il08d c-mos memory controller
?op view 120
115
110
105
100
95
90
85
80
75
70
65
61 180
175
170
165
160
155
150
145
140
135
130
125
121 1
5
10
15
20
25
30
35
40
45
50
55
60
v dd l
gnd
v dd h
gnd
gnd
v dd l
gnd
v dd h
gnd
gnd
v dd h
gnd
v dd l
gnd
gnd
v dd h
gnd
v dd l
v dd l
gnd
v dd h
gnd
gnd
v dd l
gnd
v dd h
gnd
pin no. i/o i/o i/o pin pin no. no. signal signal signal i/o pin no. signal pin no. i/o signal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 v dd l 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 144 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 210 211 212 213 214 215 216 217 218 219 220 221 209 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 i i i i i i i i i i i i i i o i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i o o i o i o o i o o o i i i i i i i i i i i o o o o o o i i i i i i i i i i i o i i i i i i i i i i i i i o o o o o o o o o o o o o o o o o o o o o o o o o o o o o i i i i i i o i i i i i i i i i i i i i i i i o i i i i/o i/o i/o i/o i/o i/o i/o i/o o i i i o o o o i i o o o o o o o o o o o o o o o o i i i i i i i i i i i m2cf m3d9 m3d8 m3d7 m3d6 gnd m3d5 m3d4 m3d3 m3d2 m3d1 m3d0 m3hd m3vd m3cf savp v dd h gnd ded9 ded8 ded7 ded6 ded5 ded4 ded3 ded2 ded1 ded0 gnd decck dehd devd decf dep dicpst dicr dicf2 dicf1 dicf0 v dd l gnd did9 did8 did7 did6 did5 did4 did3 did2 did1 did0 v dd h gnd dihd divd dip chd cvd isy hr sfthr smpp pcen v dd l gnd w27 dthp ch clpp a1d9 a1d8 a1d7 a1d6 a1d5 v dd h gnd a1d4 a1d3 a1d2 a1d1 a1d0 a1p ycer bcer rcer coe hfck gnd qtck a2d9 a2d8 a2d7 a2d6 a2d5 a2d4 a2d3 a2d2 a2d1 v dd l gnd a2d0 a2p ivst m1d9 m1d8 m1d7 m1d6 m1d5 m1d4 m1d3 m1d2 v dd h gnd m1d1 m1d0 m1hd m1vd m1cf icf0 icf1 icf2 mwy9 mwy8 v dd l gnd mwy7 mwy6 mwy5 mwy4 mwy3 mwy2 mwy1 mwy0 mwp mwfin v dd h gnd mwc9 mwc8 mwc7 mwc6 mwc5 mwc4 mwc3 mwc2 mwc1 mwc0 gnd mwck rdy9 rdy8 rdy7 rdy6 rdy5 rdy4 wrstl v dd l gnd rdy3 rdy2 rdy1 rdy0 rdp rdfin rdc9 rdc8 rdc7 rdc6 v dd h gnd rdc5 rdc4 rdc3 rdc2 rdc1 rdc0 rdrstl astb v dd l gnd mad7 mad6 mad5 mad4 mad3 mad2 mad1 mad0 mpuck v dd h gnd r27 advcf test srp refcf0 refcf1 refcf2 fntc r18 supt gnd bd9 bd8 bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 v dd l gnd bhd bvd bcf bp m2d9 m2d8 m2d7 m2d6 m2d5 m2d4 m2d3 i v dd h gnd m2d2 m2d1 m2d0 m2hd m2vd 58 59 difck 187 wr rd mwrst mrck mrrst rst CXD8818R(2/5)
a1d0 - 9 a1p a2d0 - 9 a2p advcf astb decf ded0 - 9 dehd dep devd dicf0 - 2 dicpst dicr did0 - 9 difck dihd dip divd fntc isy m1cf m1d0 - 9 m1hd m1vd m2cf m2d0 - 9 m2hd m2vd m3cf m3d0 - 9 m3hd m3vd r27 rd rdc0 - 9 rdfin rdp rdy0 - 9 rst sfthr test w27 wr input ; a/d converted y signal data parity ; advanced reference color frame ; mpu interface address strobe deck ; dif (serial digital) input cf ; dif (serial digital) input data ; dif (serial digital) input clock ; dif (serial digital) input hd ; dif (serial digital) input parity ; dif (serial digital) input vd ; forced ntsc mode ; analog component sync input ; multi-loop (1) input cf for self-diag. ; multi-loop (1) input hd for self-diag. ; multi-loop (1) input vd for self-diag. ; multi-loop (2) input cf ; multi-loop (2) input data ; multi-loop (2) input hd ; multi-loop (2) input vd ; multi-loop (3) input color frame for self-diag. ; multi-loop (3) input data for self-diag. ; multi-loop (3) input hd for self-diag. ; multi-loop (3) input vd for self-diag. ; memory read y data ; memory read r-y/b-y data ; memory read data finish block id bit ; memory read data parity ; master reset ; shifted hr input ; test mode enable ; 27mhz clock locked to analog component ; mpu interface write request ; reference 27mhz clock ; mpu interface read request ; a/d converted y signal data from digital filter ; a/d converted r-y/b-y signal data from digital filter ; a/d converted r-y/b-y signal data parity ; dif (serial digital) input composite flag (h : composite) ; dif (serial digital) input crcc error flag (h : error) ; multi-loop (1) input data for self-diag. CXD8818R(3/5) ; composite decoder input clock ; composite decoder input cf ; composite decoder input data ; composite decoder input hd ; composite decoder input parity ; composite decoder input vd
output bcer bcf bd0 - 9 bhd bp bvd ch chd clpp coe cvd dthp hfck hr icf0 - 2 ivst mpuck mrck mrrst mwc0 - 9 mwck mwfin mwp mwrst mwy0 - 9 pcen qtck r18 rcer rdrstl refcf0 - 2 savp smpp srp supt wrstl ycer input/output mad0 - 7 ; b-y signal clamp error ; buffered data ; count h timing pulse for pll ; analog component odd/even output ; clamp pulse for analog component ; dither timing pulse for a/d dither ; phase comparator pulse out for pll ; selected input signal color frame ; mpu interface clock (9mhz) ; memory write reset pulse ; memory write y data output ; phase comparate enable ; r-y signal clamp error ; memory read reset line ; reference cf ; sampling pulse for pll ; servo reference pulse ; timing pulse for set-up remover ; memory write reset line ; mpu interface data bus ; buffered cf ; buffered hd ; buffered parity ; buffered vd ; analog component hd output ; analog component vd output ; selected input signal v-start pulse ; memory read clock ; memory read reset pulse ; memory r-y/b-y data output ; memory write clock ; memory write data parity output ; y signal clamp error ; 13.5mhz clock (w27/2) for digital filter ; memory write data finish block id bit ; 18mhz clock output for player self-diag. ; 6.75mhz clock (w27/4) for digital filter ; selected input signal sav timing pulse CXD8818R(4/5)
h reset gen. gen. hd,vd clamp error detect ck transfer fifo reference h,v,cf input v cf input select memory control input data detect 151, 152 223 - 226 31 - 35 56 - 58 116 - 120 236 - 240, 1 8 - 16 209 61 isy a1d9 - a1d0, a1p a2d9 - a2d0, a2p ded9 - ded0 decck, dehd, devd decf, dep dicpst, dicr dicf2 - dicf0 dick, did9 - did0 dihd, divd, dip m1d9-m1d0 m1hd,m1vd,m1cf m2d9 - m2d0 m2hd, m2vd, m2cf m3d9 - m3d0 m3hd, m3vd, m3cf mwy9 - mwy0, mwp, mwfin mwc9 - mwc0, mwck, mwrst rdy9 - rdy0, rdp, rdfin rdc9 - rdc0, mrck, mrrst bhd, bvd, bcf, bp bd9 - bd0, mad7 - mad0 astb, wr, rd mpuck 196 183 - 185 srp 202 rst 207 hr ch w27 clpp dthp 62 70 68 71 69 3 85 - 87 supt 153, 154 output data select 200 199 advcf r27 208 r18 mpu interface 8-word hfck qtck 89 91 72 - 76, 79 - 84, 92 - 100, 103, 104 36 - 41, 44 - 53, 20 - 29, 106 - 113, 227 - 233, 2 - 5, 124, 125, 128 - 137, 140 - 149, 155 - 160, 164 - 173, 176 - 181, 211 - 220, 188 - 195, ycer, bcer, rcer CXD8818R(5/5) counter counter
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